Circuit designers of multi-Gigabit systems face a number of challenges as advances in technology mandate increased performance in high-speed components. For example, chip-to-chip data rates have traditionally been constrained by the bandwidth of input/output (I/O) circuitry in each component. However, process enhancements (e.g., transistor bandwidth) and innovations in I/O circuitry have forced designers to also consider the effects of the transmission channels between the chips on which data is sent.
At a basic level, data transmission between components within a single semiconductor device, or between two devices on a printed circuit board, may be represented by the system 100 shown in FIG. 1. In FIG. 1, a transmitter 102 (e.g., a microprocessor) sends data over channel 104 (e.g., a copper trace on a printed circuit board or “on-chip” in a semiconductor device) to a receiver 106 (e.g., another processor or memory). When data is sent from an ideal transmitter 102 to a receiver 106 across an ideal (lossless) channel, all of the energy in a transmitted pulse will be contained within a single time cell or unit interval (UI).
However, real transmitters and real transmission channels do not exhibit ideal characteristics. Due to a number of factors, including, for example, the limited conductivity of copper traces, the dielectric medium of the printed circuit board (PCB), and discontinuities introduced by vias, an initially well-defined digital pulse will tend to spread or disperse as it passes through the transmission channel. This is shown in FIG. 2. As shown, a single pulse of data 105a is sent by the transmitter 102 during a given unit interval UI (e.g., UI3). However, because of the effect of the channel 104, this data pulse becomes spread 105b over multiple UIs at the receiver 106, i.e., some portion of the energy of the pulse is observed outside of the UI in which the pulse was sent (e.g., in UI2 and UI4). This residual energy outside of the UI of interest may perturb a pulse otherwise occupying either of the neighboring UIs, in a phenomenon referred to as intersymbol interference (ISI). As shown, residual energy appearing before the UI of interest (i.e., in UI2) comprises pre-symbol ISI, while residual energy appearing after the UI of interest (i.e., in UI4) comprises post-symbol ISI.
Because ISI can give rise to sensing errors at the receiver 106, a number of solutions have been proposed to compensate for the effects of ISI (e.g., by offsetting the effects of ISI). On the transmitter 102 side, an equalizer 108 (an equalizer is sometimes also referred to a filter; these terms are interchangeable) may be employed to compensate for the anticipated effects of the channel 104. Such an equalizer 108 attempts to pre-condition the transmitted signal such that the effect of the channel 104 is removed. One such technique comprises the use of finite-impulse response (FIR) filters. See, e.g., R. W. Lucky et al., “Automatic equalization for digital communication,” in Proc. IEEE, vol. 53, no. 1, pp. 96-97 (January 1965); R. W. Lucky and H. R. Rudin, “Generalized automatic equalization for communication channels,” in Proc. IEEE, vol. 53, no. 3, pp. 439-440 (March 1966); S. Reynolds et al., “A 7-tap transverse analog-FIR filter in 0.13 μm CMOS for equalization of 10-Gb/s fiber-optic data systems,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 330-331 (February 2005); M. E. Said et al., “A 0.5-μmSiGe pre-equalizer for 10-Gb/s single-mode fiber optic links,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 224-225 (February 2005); and J. E. Jaussi et al., “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 80-88 (January 2005). Such an FIR filter 108 performs processes known as pre-emphasis or de-emphasis in which the signal is intentionally pre-distorted before it is transmitted to compensate for the anticipated effects of the channel 104. An FIR filter 108 may alternatively be employed on the receiver side 106 to compensate for effects of the channel. Unfortunately, FIR filters typically require multiple taps to compensate for the losses in a channel, resulting in larger, more power-hungry, and more complicated circuitry.
Alternatively, on the receiver 106 side, an equalizer 109 may be used to compensate for the effects of the channel 104, including ISI. The transfer function of an ideal equalizer is the inverse of the transfer function of the channel 104, and a practical equalizer attempts to recreate this inverse frequency response. One such ISI-mitigating technique includes the use of a decision feedback equalizer (DFE) 109 at the receiver 106 side of the transmission. See, e.g., M. E. Austin, “Decision-feedback equalization for digital communication over dispersive channels,” Massachusetts Institute of Technology: Research Laboratory of Electronics, Cambridge, Tech. Rep. 461 (1967); M. Sorna et al., “A 6.4-Gb/s CMOS SerDes core with feedforward and decision-feedback equalization,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 62-63 (February 2005); R. Payne et al., “A 6.25-Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications,” in Proc. IEEE Int. Solid-State Circuits Conf., pp. 68-69 (February 2005); J. W. M. Bergmans, “Digital magnetic recording systems,” IEEE Trans. Magn., vol. 24, pt. 1, pp. 683-688 (January 1988); and R. S. Kajley et al., “A mixed-signal decision-feedback equalizer that uses a look-ahead architecture,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 450-459 (March 1997). A DFE presents an attractive solution as it is fairly resistant to high-frequency noise amplification, and further provides a variable detection threshold that may be designed to follow shifts or trends in data resulting from ISI. However, DFEs are more difficult to implement than FIR filters in the multi-Gigahertz frequency range due to the necessary reliance on feedback from past decisions, and the need to employ multiple taps.
A third equalization option comprises the use of a continuous-time equalizer (CTE). See, e.g., B. K. Casper et al, “A 20 Gb/s Forwarded Clock Transceiver in 90 nm CMOS,” Proceedings of the IEEE International Solid State Circuit Conference, San Francisco, Calif., pp. 263-272 (February 2006); Y. Tomita et al., “A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-μm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 986-993 (April 2005); J. E. C. Brown et al., “A CMOS adaptive continuous-time forward equalizer, LPF, and RAM-DFE for magnetic recording,” IEEE J. Solid-State Circuits, vol. 34, no. 2, pp. 162-169 (February 1999); James E. C. Brown, “Continuous-Time Forward Equalization for the Decision-Feedback-Equalizer-Based Read Channel,” IEEE Transactions on Magnetics, Vol. 34, No. 4, pp. 2372-81 (July 1998); and H. Higashi et al., “A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization,” IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 978-985 (April 2005).
One type of continuous-time equalizer (CTE) 109 implementable at the receiver 106 is illustrated in FIGS. 3A and 3B, which depicts circuitry disclosed in James E. C. Brown and Paul J. Hurst, “Adaptive Continuous-Time Forward Equalization for DFE-Based Disk-Drive Read Channels,” 29th Asilomar Conference on Signals, Systems and Computers, pp. 668-672 (1996), which is incorporated herein by reference in its entirety. In FIG. 3A, the input signal, IN, is input to the CTE 109 from the channel 104. As shown in FIG. 3B, this input signal has been dispersed by ISI. Such dispersion in the input signal IN can be modeled as a Lorentzian pulse, which is governed by the following formula:IN(t)=1/[1+(2t/W)2]where W equals the pulse width at half the maximum amplitude.
In the depicted CTE 109, the input signal is split, with one leg being sent to a differentiator block 110. Thereafter, the original signal and the differentiated version of the original signal are scaled (e.g., weighted) by κ and α respectively, and then the differentiated version is subtracted at a subtractor 111. (As shown in this disclosure, subtraction functionality is portrayed as being performed by an adder with a negative input, such as is seen in the lower leg in FIG. 3A. This representation for subtraction is used to make clear which input is subtracted from which). When the scalars κ and α are chosen appropriately, the effect is to reduce pre-cursor ISI in the resulting output signal. This is shown by a reduction in the prominence of the rising edge in the produced output signal, OUT, as shown in FIG. 3B.
This approach of Brown & Hurst should reduce pre-cursor ISI as stated. However, the CTE 109 of FIG. 3A does not address, and does not attempt to address, post-cursor ISI. In fact, the Brown & Hurst article addresses minimization of post-cursor ISI using an entirely different circuit, namely a multi-tap DFE circuit, similar to those discussed above. In this respect, the present inventor has determined that the approach of Brown & Hurst is inefficient, as it requires two different circuits (a CTE and a DFE) to address both pre-cursor and post-cursor ISI, which essentially doubles the effort needed to engineer, lay out, and optimize a comprehensive ISI mitigation solution.
Another CTE implementation was posited in Richard Schneider, “An Improved Pulse-Slimming Method for Magnetic Recording,” IEEE Transaction of Magnetics, Vol. 11, No. 5, pp 1240-41 (1975), which is incorporated herein in its entirety. While not specifically noted as a circuit useful to counter ISI, Schneider's equalizer circuit has the capability of “slimming” both the rising and falling edges of a pulse in real time, and so is usable to mitigate both pre-cursor and post-cursor ISI. As shown in FIG. 4, Schneider illustrates his equalizer circuit 109′ in the Laplace domain, which is related to the frequency domain through the relationship ‘s’=‘jw’, where ‘w’ is the radian frequency. Schneider's equalizer 109′ comprises two stages 114a and 114b, which respectively slim the falling edge and the rising edge of the input signal, IN. As one skilled in the art will appreciate, a single ‘s’ term, as appears in blocks 116a and 116b, comprises a first order derivative (d/dt). Accordingly, each of blocks 116a or 116b are equivalent to the scaled differentiator 110 of FIG. 3A, where once again the derivatives are scaled by alpha terms α1 and α2 respectively. Stage 114a mitigates post-cursor ISI through its use of an adder 115a, while stage 114b mitigates pre-cursor ISI (similar to Brown & Hurst's approach; FIG. 3A) through its use of a subtractor 115b. 
Schneider's equalizer 109′ is in one sense a preferable circuit to use in the mitigation of ISI because, as previously noted, Schneider's circuit can reduce both pre-cursor ISI and post-cursor ISI. That being said, the present inventor has determined that the equalizer circuit 109′ has shortcomings. Specifically, and unlike the approach of Brown & Hurst's equalizer 109 (FIG. 3A), Schneider's equalizer 109′ does not allow for the scaling of the input signal. Instead, Schneider's circuit 109′ only allows for the scaling of the derivatives, i.e., by α1 and α2. In other words, the circuit 109′ does not allow for the scaling of the undifferentiated part of the input signal, as was the function of scalar κ in Brown & Hurst's circuit 109. The present inventor considered this unfortunate, because, the inability to scale of the input signal reduces design flexibility, which ultimately hampers flexibility to reduce ISI. This is significant because, depending on the factors causing dispersion in the channel 104, it may be advantageous for the design to be able to equalize pre-cursor ISI with more or less severity than post-cursor ISI. Moreover, in today's high-frequency systems, Schneider's approach, which uses serially-connected stages 114a and 114b, adds undesirable delay and phase shift to the input signal, IN.
A better, more flexible, and easier to implement equalization solution, capable of mitigating both pre-cursor and post-cursor ISI, is therefore desired.